1. Field of the Invention
This invention is related to the field of digital integrated circuits and, more particularly, to clock gating in integrated circuits.
2. Description of the Related Art
As electronic circuits, and particularly integrated circuits, increase in density, power consumption also increases. Power management circuitry is often implemented in integrated circuits to reduce power consumption. For example, power management circuitry can be used to selectively and/or temporarily remove power from a portion or all of an electronic circuit during times that the portion is inactive. Alternatively or in addition, power management circuitry can include conditional clocking circuitry (also known as clock gating circuitry or a clock gater).
Conditional clocking generally includes conditionally generating a clock to a functional circuit dependent on whether or not the functional circuit is active. If the circuit is active, the clock is generated (e.g. rising and falling edges are generated providing a high phase and a low phase of the clock signal). If the circuit is inactive, the clock is inhibited (e.g. held in a constant state, high or low, instead of toggling). Inhibiting the clock during idle times for the functional circuit results in power savings since the state of the circuit is held steady and thus the circuit experiences minimal switching activity. Typically, an enable input to the conditional clock circuitry controls whether the clock is generated or inhibited. The clock can also be inhibited even if the functional circuitry is active, in order to decrease power consumption.
The timing constraints on the enable input to the clock gater are often challenging. For example, an AND gate may be used to generate a conditional clock (with one input being the input clock and the other being the enable signal). In this case, the setup time for the enable signal is relatively short, but the hold time is approximately one half clock cycle (since the enable signal is required to remain valid, either high or low, for an entire phase of the input clock along with margin on each side to ensure glitch-free operation). As another example, an AND gate with a passgate latch on the enable signal input can be used. While the hold time may be shorter than the single AND gate (e.g. approximately the hold time of the passgate latch), the setup time is lengthened since the enable signal must propagate through the passgate latch prior to the rising edge of the input clock.